1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a vertical fuse and method for reducing semiconductor chip layout area.
2. Description of the Related Art
Semiconductor devices such as memory devices include fuses within their structure. In dynamic random access memory (DRAM) chips, the number of fuses increases significantly for each new generation of DRAM chip designs due to increases in memory density. In conventional DRAM designs, fuses either laser blown or electrically blown, are disposed parallel to the chip direction. This orientation will be called horizontally disposed fuses or horizontal direction fuses. Horizontally disposed fuses consume roughly 3% of the total chip area together with fuse circuitry.
One use for fuses in memory devices is to activate/deactivate areas or blocks of the chip. This may be done using anti-fuses and fuses, respectively. For example, to improve chip yield redundancies are employed which are activated by blowing fuses. For next generation DRAMs the areas for fuses will be increased significantly due to, among other things, increased redundancy. For example, if a conventional DRAM chip included 15,000 fuses, a next generation DRAM chip may include about 30,000 to about 50,000 fuses.
The present invention provides a vertically disposed fuse which may advantageously by formed without additional process and mask steps, along with metal structures of a semiconductor device. The following is a brief description of the formation of contacts/metal lines for a dual damascene process.
Referring to FIG. 1, a semiconductor device 10 is shown. Semiconductor device includes a substrate 12. A dielectric layer 14 is deposited and patterned according to processes know in the art. Dielectric layer 14 may include an oxide such as TEOS or BPSG. A conductive material 16 is deposited on dielectric layer 14. Conductive material 16 includes a metal such as tungsten or aluminum. Conductive material 16 forms metal lines or other conductive structures, for example at an MO level of a dynamic random access memory chip.
Referring to FIG. 2, a dielectric layer 18 is deposited on dielectric layer 14 and conductive layer 16. Dielectric layer 18 is an oxide such as silicon dioxide. Dielectric layer 18 is patterned and etched to form a contact hole 20 and metal line trench 22 for a dual damascene deposition of a conductive material 24 such as aluminum as shown in FIG. 3. A chemical mechanical polishing (CMP) is performed to planarize a top surface and remove conductive material 24 from the surface.
Referring to FIG. 4, a dielectric layer 26 is deposited on dielectric layer 18 and over a contact/metal line 28 formed in dielectric layer 18. Dielectric layer 26 is preferably an oxide such as silicon dioxide.
Referring to FIGS. 5 and 6, dielectric layer 26 is patterned and etched to form a via hole 32 and metal line trench 34 for a dual damascene deposition of a conductive material 36 such as aluminum to form a via/metal line 38 as shown in FIG. 6. CMP is performed to planarize the top surface and remove conductive material 36 from the surface.
The process described in FIGS. 1-6 is performed across semiconductor device 10. Contact/metal line 28 and via/metal line 38 are formed within a memory array portion 30 of a memory chip, for example.
Therefore, a need exists for reducing the area occupied by fuses on a semiconductor chip. A further need exists for a method of adjusting the fuse resistance for the fuses in a semiconductor device. A still further need exists for fabricating fuses without the additional process steps and masks.